1. Field of the Invention
The invention relates to a voltage controlled oscillator, and more particularly to a low-voltage, low jitter voltage controlled oscillator.
2. Description of the Related Art
Due to the great progress of the semiconductor technology, the operating speed of contemporary computers is getting increasingly faster. However, the increase of the operating speed results in more power consumption. To efficiently reduce the power consumption, the operating voltage of contemporary computers is gradually lowered from 5V to 2.5V, even to less than 2.0V. In coordination with the decrease of the operating voltage, a large number of circuits must be further modified to allow themselves to work at low-voltage condition, for example, an oscillator for providing a clock signal. Furthermore, clock signals used in current computer system have different frequencies. Most of the clock signals with different frequencies are proportionally generated based on a reference clock signal by a phase-locked loop circuit for the use of a number of sub-systems. A voltage controlled oscillator in the computer system is one of the main factors to affect the performance of the phase-locked loop circuit. Additionally, the performance of the voltage controlled oscillator can be estimated based on long-term jitter, short-term jitter and influences caused by the variation of the power supply voltage.
FIG. 1 is a circuit diagram illustrating a conventional voltage controlled oscillator.
Referring to FIG. 1, the conventional voltage controlled oscillator is a closed loop circuit, and includes 3 inverters 111, 112 and 113 electrically connected in series. A control voltage VC is used to control each inverter to determine a signal delay time between the input terminal and the output terminal thereof. Thus, the frequency of a generated output signal VO can be determined by controlling the delay time.
FIG. 2 is a circuit diagram illustrating a conventional voltage controlled oscillator 200 consisting of MOS FETs.
As shown in FIG. 2, the voltage controlled oscillator 200 is a closed loop circuit consisting of 3 inverters which are constituted by MOS FETs 211, 221, MOS FETs 212, 222 and MOS FETs 213, 223, respectively. A control voltage VC is input to the gates of the MOS FETs 211, 212 and 213 for controlling the response time of each inverter, thereby determining the frequency of the output signal VO of the closed loop circuit.
As described above, the frequency of the output signal VO generated by voltage controlled oscillator 200 can be controlled by control voltage VC. However, the characteristics of the voltage controlled oscillator are easily affected by the variation of a power source Vps to vary the frequency of the output signal because each inverter consists of only two MOS FETs.
FIG. 3 is a circuit diagram illustrating a delay unit 300 of another conventional voltage controlled oscillator. Similarly, the conventional voltage controlled oscillator is also a closed loop circuit consisting of 3 inverters.
Compared to the prior inverter having only one input terminal and one output terminal, the delay unit 300 shown in FIG. 3 has not only an input terminal IN and an output terminal OUT, but also a complementary input terminal IN and a complementary output terminal OUT for reducing sensitivity to the variation of power source Vps. In delay unit 300, MOS FETs 311 and 312 constitutes a latch circuit MOS FETs 321 and 322 connected in the form of a diode serve as active load devices. MOS FETs 331 and 332 are used for differential inputs, wherein the gates thereof serve as an input terminal IN and a complementary input terminal IN. A MOS FET 340 is controlled by a control voltage VC to provide a drain current (current source) directly proportional to the control voltage VC, thereby determining the delay time of the delay unit. Therefore, the frequency of an oscillating signal generated by a closed loop circuit consisting of multiple delay units can be controlled by the control voltage.
Although the voltage controlled oscillator consisting of the delay units 300 has a better performance, 3 layers of MOS FETs stacked on each other between the power source Vps and ground need a higher operating voltage. The drain current of each MOS FET can be given by: ##EQU1##
The lowest operating voltage required by delay unit 300 is 2V.sub.t +3.DELTA.V, wherein .DELTA.V=V.sub.gs -V.sub.m.
As can be seen from the above, a required operation voltage must be greater than 2.7V, if .DELTA.V=0.3V, and V.sub.t =0.9V. However, since the power source of a current computer system can be as low as 2.5V, even less than 2.0V, the delay unit 300 can not normally operate in this case.
Accordingly, the prior art has the following disadvantages:
1. The first conventional voltage controlled oscillator has a simple structure, but the frequency of an generated oscillating signal is easily affected by the variation of the power source.
2. The second conventional voltage controlled oscillator has a better performance. However, it needs a higher operating voltage such that it can not meet the requirements of a computer system that uses a lower power source voltage.